Video of calibrated bit available!

This video demonstrates the circuitry of one bit of the D/A proposed.( unfortunately, the quality is not good, but I'll fix it really soon!)

Advantages of the proposed architecture

Have you ever wondered how a DAC would look like, that provides the speed of the classical R2R laser trimmed version but  without the excessive costs of the trimming procedure? Well the answer is here:

The proposed DAC provides:

1. speed comparable to the R2R ladder
2. easy to implement MOSFET ladder topology
3. easy calibration of each bit resulting in lower INL and DNL errors
4. low power consumption
5. easy expendability through card slots

but what is the most important feature of it all, is that the greater the variance of the  Mosfets are, the better linearity achieved via the innovative calibration process! This translates to lower cost design compared to solutions currently on the market!